9/26/2023 0 Comments Xilinx ise 14.7 missing .idata.binSignal row_index,col_index : integer := 0 Signal data_rom,data_in_ram,data_out_ram : STD_LOGIC_VECTOR ( 7 DOWNTO 0 ) := ( others => ' 0 ' ) Signal addr_rom,addr_ram : STD_LOGIC_VECTOR ( 3 DOWNTO 0 ) := ( others => ' 0 ' ) Signal wr_enable : STD_LOGIC_VECTOR ( 0 DOWNTO 0 ) := "0" Wea : IN STD_LOGIC_VECTOR ( 0 DOWNTO 0 ) ĭina : IN STD_LOGIC_VECTOR ( 7 DOWNTO 0 ) Architecture Behavioral of image_process isĪddra : IN STD_LOGIC_VECTOR ( 3 DOWNTO 0 ) ĭouta : OUT STD_LOGIC_VECTOR ( 7 DOWNTO 0 )
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